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In China, existing line selection devices theoretically use high-order zero-sequence currents (mainly five times) to achieve fault line selection. However, due to the small proportion of the harmonic components used in the device in the signal, it is difficult to separate and extract, and the harmonic interference of the load makes the device based on the principle of harmonics misjudge in actual operation. Most of the rest of the line selection methods are based on the analysis of the steady state signal after the fault, but the small current grounded grid has a small ground current in steady state, which reduces the accuracy of the protection line selection based on amplitude comparison, and the protection based on phase comparison is prone to error. Select [2,3]. In view of these problems and the actual production needs, we designed this fault line selection device. It uses wavelet transform to extract the characteristic components of the transient catastrophe signal, and uses the transient information to select the line. It solves the problem of traditional line selection methods using steady-state information for low line selection accuracy and enhances the anti-interference ability. In addition, the device is applicable to all small-current grounding systems, including a small-current grounding system equipped with only two-phase current transformers, which overcomes many of the previously proposed line selection methods that fail when only two-phase current transformers are installed in the system. defect.
1. The principle of software and hardware design of the system
The main reason for difficulty in line selection of small-current grounded networks is that the fault current is line-to-ground capacitive current when the single-phase grounding is connected. The value is very small, and the variation before and after the fault is very weak. In addition, the single-phase ground fault condition is complicated and the length of the different systems is different from the feeder length. The neutral point grounding method and other aspects are quite different, and the system operation mode is changeable, requiring a high flexibility and adaptability of the line selection device [4].
1.2 Wavelet Algorithm [5 ~ 7] Wavelet analysis is a new type of time-frequency transformation theory. The biggest difference between it and Fourier analysis lies in adding a “time frequency†window to the signal to be processed, and it can automatically Adjust the size of the window to ensure that you capture the desired information in the signal. At the same time, the wavelet transform is particularly effective for analyzing mutated signals. This is what the Fourier analysis failed. Since a single-phase ground fault signal may contain many spikes or abrupt changes, as well as many noise disturbances, the use of traditional Fourier transform analysis is powerless for denoising non-stationary signals, because Fourier analysis is to completely eliminate signals. Analysis in the domain, any mutation of the signal on the time axis will affect the entire spectrum of the signal. The wavelet analysis can analyze the signal in the time-frequency domain at the same time, and there is an "auto-zoom" function, so it can effectively distinguish the abrupt part of the signal and the noise.
In practice, continuous wavelets need to be discretized. This discretization is for continuous scale parameter a and continuous shift parameter b, not for time variable t. The corresponding discrete wavelet function ψj,k(t):
The device uses wavelet transform to decompose a signal into wavelets of different scales and positions. Wavelet and wavelet bases are used to carry out wavelet transform on the characteristic components of transient currents, and then the wavelet transform of the transient signals of each line is compared with the principle of wavelet transform modulus maxima. To achieve fault line selection. From the amplitude point of view, the current traveling wave signal of the non-faulty line is only the transmission component of the traveling wave of the faulty line, so the corresponding wavelet transform modulus maximum is also small, while the current line wave signal of the fault line is under the wavelet transformation. Its modulus maximum is the largest. The line selection is initiated by the variation of the zero-sequence voltage (U0). The sudden change of U0 is the time of the fault. The specific line selection scheme is as follows.
1) Due to the existence of electromagnetic coupling between parallel multi-wires, phase mode conversion can be used to decouple them for analysis and calculation. For phase A and phase C faults, the current data of the first and second phases of the phase A and phase C faults are taken and calculated. The β-mode current [8]; for the B-phase fault, take the A-phase current before and after the two-cycle fault data and calculate the mutation.
2) A threshold selection algorithm based on Stein's unbiased risk estimation theory [9] is used to de-noise β-mode currents (A and C phase faults) or phase A current (B-phase faults) of n lines.
3) Then according to Mallat algorithm, use Daubechies3 wavelet to carry out multi-scale wavelet transform on the de-noised signal. The scale wavelet coefficients of each scale are defined as cdjk(j=1,2,...,x;k=1,2,...,n ). Among them, j is the decomposition scale, x is the decomposition scale of the power frequency component in the wavelet decomposition frequency band, and k is the line number.
4) Calculate the respective return lines |cdjk|, calculate the wavelet decomposition scale j where each line is the largest, and define the subspace where j is relatively dense as the line selection space.
5) Find the module maxima of the wavelet transforms in the same line selection space for each line and compare them, and compare the first three which have the largest amplitude values ​​with each other. If one is opposite to the other two, judge the maximum value. The line is grounded, otherwise the bus is grounded.
2 system hardware design
2.1 Hardware Schematic In order to ensure the realization of the above functions, the functional components and composition of the device.
2.2 Hardware Design In order to ensure the high accuracy of the system measurement and the reliability of the operation, the following work has been done on the design of the hardware circuit:
1) The host adopts PC-class industrial control computer, which is characterized by high reputation of the manufacturer, mature technology and good versatility, and is suitable for making general-purpose products.
2) The input frequency response of the current transducer is in the range of 25Hz to 5kHz and the accuracy level is 0.1. With AC and DC common, high precision, high isolation, wide frequency response, fast response time, low drift, low power consumption, wide temperature range and other characteristics [10].
3) To prevent signal aliasing, the current signal is filtered by the MAX274 low-pass filter to remove high-frequency components of the signal before A/D sampling. MAX274 is an 8th-order continuous-time active filter introduced by MAXIM in the United States. It contains a number of (2) MAX274 4th-order state variable filter units. It requires no external capacitor and only requires an external resistor. A low-pass, band-pass filter that operates from 100Hz to 150kHz. Its center frequency, turning frequency, Q value, magnification, etc. can be determined by external resistance, and parameter adjustment is very convenient.
4) The data acquisition card uses a self-designed data acquisition card with a TMS320-VC5402 DSP as the CPU. Since the criteria for line selection mostly depend on the current values ​​at the same time of each outgoing line, simultaneous sampling techniques are needed to simultaneously perform multi-channel signals. Sampling is performed so that the phase relationship between the measured signals is consistent with the original signal. We use the MAX125ADC from Maxim to achieve simultaneous acquisition of multiple channels. The MAX125 is a high-speed multi-channel 14-bit parallel data acquisition chip with internal synchronous sample and hold. The chip contains a 14-bit, successive-analog-to-analog converter with a single-channel conversion time of 3μs. A set of sample/hold circuits that can simultaneously sample four input signals simultaneously. The MAX125 has an alternate switch in front of each sample/hold circuit so that there are a total of eight input channels (groups A and B), but only one of them can be sampled at the same time each time. , 12]. In practical applications, three MAX125s are simultaneously activated by the XF pin of the TMS320VC5402 or an external clock signal for A/D conversion. When 3 MAX125
Take 3 pieces of MAX125 each 4 times, can read the result after conversion, achieve the function that realizes and collects to 12 signals at the same time.
2.3 Acquisition board principle The part in the dashed box in Figure 3 is the hardware block diagram of the sampling processing unit. It uses C5402DSP as CPU, mainly consists of 1) peripheral auxiliary circuit 2) program/data memory 3) analog input channel 4) switch input/output channel 5) communication serial port 6) C5402 and PC industrial computer communication interface circuit and other six parts composition.
The use of the C5402DSP as the CPU is to reduce the burden of continuous sampling on the system. For example, the sampling rate is 10k. In the case of no hardware buffer device, the interruption period is 1/10k=100μs. Traditional operating systems such as Windows and Linux are mainly designed for multitasking. The scheduling subroutines are mainly The method of averaging time slots is used to solve multi-tasks. The base value unit of this time slice is called the global variable jiffies. In traditional operating systems, this value is generally around 10 ms. Obviously, it is difficult to meet our requirements. Corresponding to the above situation under normal circumstances, the common acquisition board processing method is to add FIFO. The FIFO is a first-in, first-out memory, and AD sequentially writes data, and the user can read the data in real time at the same time. The flag bits normally used in the FIFO are: "Half Full-HF" and "Overflow-FF". When the FIFO is operated with HF=0, the user can continuously read out the sampling data at a time, and the non-stop AD writes data to the FIFO. If the FF FF bit is 0, it indicates that the FIFO overflows and the read data will lose data, so the user must keep the FIFO from overflowing. However, this method of adding FIFO can only suspend the problem of interruption and cannot solve the problem fundamentally.
The following is an example of an ordinary acquisition board with FIFO capacity of 1k, 8-channel A/D and sampling rate of 10k:
The number of points collected during each interruption is N=512/8=64; the interruption interval T=64/10000=6.4ms.
It can be seen that if the sampling rate is so high or higher, it is difficult for the general operating system to run stably. Another problem that arises when using FIFO at the same time is the real-time determination of the fault. After using the FIFO, it is necessary to determine the fault at intervals. It is difficult to accurately locate the fault point when the fault signal has no obvious sudden change. However, the above problem does not exist for the current acquisition unit because the TMS320VC5402 adopts an enhanced Harvard architecture. The eight internal buses allow the chip to maximize its processing capability. The independently addressable 64k data space and 1M program space allow simultaneous access to program instructions and data. The six-stage pipeline operation guarantees a processing speed of 100 MIPS (millions of instructions per second). This is fully qualified for the general required sampling rate, which allows for point-by-point calculations of the acquired data to greatly improve accuracy and accuracy [13].
2.4 Implementation of Communication between Acquisition Board and Host
This system is a master-slave type structure, the host is a PC industrial control machine, and the slave is a TMS320VC5402 DSP. They establish a connection through a PC ISA bus. The PC can read and write its on-chip RAM storage unit through the HPE port of the C5402, and the C5402 can't read or write the host's storage unit. The two parties use the interrupt mode to communicate with each other. When a conventional MCU interfaces with an external host, it is necessary to externally expand necessary hardware circuits. When the microcontroller needs to share RAM with the host, it needs to extend the RAM, trigger, and latch the chip outside the chip, and then the host accesses the expansion RAM through DMA, so that the host can access or share the RAM randomly or in a block. In addition, at least one latch must be extended outside the chip so that the microcontroller can interrupt the host. TI's TMS320C5402HPI interface integrates the above functions into the DSP, making it easy to connect to the host. And because HPI is integrated into the chip, the host can achieve high access speeds and meet the high speed requirements in digital signal processing. In practical applications, the PC sends some control commands and data to the C5402, which mainly includes:
1) Sampling command to control start and stop of C5402 sampling;
2) The parameter modification command informs C5402 to modify the parameters and setting values;
3) Data upload command to notify C5402 to upload sampling data.
At the same time, C5402 should also inform the PC of its own operating status and detected information, including:
1) normal operation;
2) Fault startup status.
In order to achieve the above two-way information exchange, two storage units can be defined in the internal RAM of the C5402. One is a command unit for storing command words sent from the PC to the C5402, and the other is a status unit for storing the symbol C5402 system. State of the status word. In addition, two storage areas are divided from the internal RAM of the C5402. One is a Host area for storing data transmitted from the PC to the C5402, and the other is a Slave area for storing data to be transmitted to the PC by the C5402. When the PC wants to send commands and data to the C5402, it first writes the command word and data into the command unit and the Host area, and then sends an interrupt request signal to the C5402. After the C5402 responds to the interrupt, the command word and data are read out and commanded. The word completes the corresponding operation. The PC can read the status unit at any time to obtain the status information of the C5402 system. In normal operation, the value of the C5402 status word is initialized to 0000H. After the fault occurs, when the C5402 needs to upload necessary data information to the PC, the status word and data are written into the status unit and the Slave area, and an interrupt request is sent to the PC. After the PC responds to the interrupt, the status word and data are read. Out, and according to the status word to complete the appropriate operation.
2.5 Experimental verification of the acquisition board
In order to verify the correctness of sampling and processing units and to be used in fault line selection devices, the following experiments were completed. The test signal is generated by a signal generator: sinusoidal signals with levels of -1V to 1V and frequencies of 50Hz and 200Hz, respectively. During the test, the A/D sampling clock signal was generated using the XF pin of the DSP. The sampling frequency was set by the DSP's internal timer and was 1.6 kHz. For a 200 Hz input signal, 8 points are sampled in one cycle; for a 50 Hz input signal, 32 points are sampled in one cycle. The sampled data is stored in the DSP's internal RAM, which is then read by the IPC via the ISA bus, saved to the hard disk as a file, and finally displayed in MATLAB. It can be seen that the sample recovery waveform coincides with the original waveform and is very smooth. Through the above tests, it can be affirmed that the design of the sampling and processing unit is successful.
3. The main functions and features of the device
1) Under normal conditions, the device monitors the zero-sequence voltage (U0) variation in real time and does not perform any analysis on the sampling data. When a single-phase ground fault occurs, the monitoring program issues a command and the hardware triggers the device. The device then saves the data in the current data window, downloads the collected data to the hard disk of the computer and starts the line selection algorithm, and gives the line selection result.
2) Failure phase selection. If the lowest voltage phase voltage is less than K times the rated phase voltage, the lowest voltage phase is the ground phase; if the three phase voltage is greater than K times the rated phase voltage, the next phase of the highest voltage phase is the ground phase; in the actual fault phase The K value in the judgment should be less than 0.823. Neutral arc suppression coil grounding system to distinguish the fault phase and neutral point ungrounded system is similar to the above method of "the next phase" to "the previous phase" can [14].
3) Determine the fault line, issue a line selection signal or trip. If the fault cannot be determined using the transient method, the steady-state method is started for calculation: FFT decomposition of the sampled values, queuing by fundamental or 5th harmonics (using fundamentals for NUS and NRS, harmonics for NES), The first three with the largest amplitude perform the phase comparison. If one is opposite to the other two, the line is judged to be grounded. Otherwise, the bus is grounded.
4) Each data acquisition board can monitor 12 lines at the same time.
4 Conclusion
When single-phase grounding occurs in a small-current grounding system, the frequency, amplitude, and phase parameters of the fault current transient have a clear correlation with the fault characteristics. The transient component of the grounding capacitor current is often several times larger than its steady-state value. Dozens of times, the device adopts the wavelet analysis theory of the line processing algorithm that can accurately process the mutated and faint non-stationary fault signal. The line selection algorithm solves the traditional line selection method and uses the steady state information to select the line accurately. The low problem, in addition to the fault line selection device to monitor multiple lines at the same time and collect multi-channel power information, data analysis and processing tasks are arduous. The digital signal processing chip (DSP) has fast calculation ability and powerful data processing capability, and can provide powerful hardware support for fault line selection. For this purpose, a real-time multi-channel synchronous data acquisition system is constructed using a DSP to ensure synchronization, real-time performance, and accuracy of the multi-channel signal measurement. The implemented device can meet the needs of actual operation.
Design of New Type Low Current Grounding Fault Wire Selection Device
The distribution network neutral point adopts a small current grounding method with a series of advantages, so it is adopted by power distribution systems in many countries. However, since the fault current is very small when the single-phase grounding of the small-current grounded power grid is very small, the single-phase grounding protection problem has not been well solved. In fact, using conventional relay protection devices can not detect fault lines at all, and fault line selection must use dedicated line selection devices. This special device was born in China in the 1980s, but due to the complexity of the line selection problem, the accuracy of the line selection of these devices is very low, so that we must use manual routing methods.